This invention relates to a semiconductor memory device having a three-dimensional memory cell array structure in which columnar element rows are arranged at high density in the electrode-stacked direction with respect to stacked electrode films.
A conventional stacked memory technology has many production steps per layer and is not suitable for enlargement of capacity, by the structure in which layers are stacked by repeating a step of forming a general plane memory cell on a silicon substrate at times of the number of the layers.
Accordingly, there is proposed a technique that though a stacked structure in which gate electrode layers and interlayer insulator layers are alternately stacked, holes passing from the uppermost layer to the lowermost layer are opened at one time and that silicon containing impurities is buried in a columnar shape and thereby enlargement of capacity is achieved by high production efficiency (Patent document 1 (JP-A 2007-266143 (Kokai)).
In this case, the structure is that the gate electrode layers cover the pillar of silicon by a certain interval, and a charge trap layer for data storage is provided in the crossover part between the gate electrode layer and the silicon pillar, and thereby, the memory cell transistor is formed. However, in forming a through-hole in the multilayer structure of the electrode layers and the insulator layers at one time, the diameter of the through-hole, namely, the diameter of the silicon pillar buried into the hole tends to be narrower in the lower part, and therefore, the problem that the characteristics of the memory transistor become different between the upper layer side and the lower layer side is feared.